1. Technical Field
The present invention is generally related to a reconfigurable sorter with low timing latency; in particular to the sorting device with a plurality of serially-connected comparison units and method of sorting.
2. Description of Related Art
Sorter is one of the important tools for numerical computation operated in a processor no matter it is made by software or hardware. According to a rough investigation, the operations made by the sorter may be accounted for around a quarter of the computing resources, including time and memory. It is therefore an important issue that how to improve the sorting algorithm.
One of the prior arts may be referred to U.S. Pat. No. 5,440,736, filed on Nov. 24, 1993, which is directed to a sorter for records having different amounts of data. Before the operation of this sorter for processing the different amounts of data, the collection of records is required to be normalized. The data may be categorized into different subsets. The data in every subset is firstly sorted in parallel, and the data of sorted subsets are then merged after one more sorting. However, this approach may meet timing latency and require much complicated hardware while the data goes through the mentioned process of grouping, sorting, and a final sorting.
One further prior technology is such as U.S. Pat. No. 5,535,384, filed on Jun. 8, 1994, which discloses a method for controlling a hardware merge sorter. This sorter may handle a large amount of data. The sorter is associated with multiple processors, memories, and selectors. The sorting system may be able to handle the large amount of data by paralleling the pipeline merge sorting circuits.
Referring to the above-mentioned prior technologies, the conventional sorting tasks require much complex hardware design to reduce timing latency. That means the lesser complex hardware design may result in longer timing latency. Further, the conventional sorter has no re-configurability.